This example describes a 64-bit x 8-bit dual clock synchronous RAM design with separate read and write addresses in VHDL. Synthesis tools are able to detect RAM designs in HDL code and automatically infer the altsyncram or altdpram megafunctions depending on the target device architecture.
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Table 1. Dual Clock Synchronous RAM Port Listing
Port Name |
Type |
Description |
|---|---|---|
data[7:0] |
Input |
8-bit data input |
raddr[5:0] |
Input |
6-bit read address input |
waddr[5:0] |
Input |
6-bit write address input |
we |
Input |
Write enable |
rclk |
Input |
Read clock |
wclk |
Input |
Write clock |
q[7:0] |
Output |
8-bit data output |