Verilog HDL: Unsigned Multiplier

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This example describes an 8 bit unsigned multiplier design in Verilog HDL. Synthesis tools detect multipliers in HDL code and infer lpm_mult function.

Figure 1. Unsigned multiplier top-level diagram.

Table 1. Unsigned Multiplier Port Listing

Port Name

Type

Description

a[7:0], b[7:0]

Input

8 bit data inputs to multiplier unit

out[15:0]

Output

16 bit multiplier output
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