Verilog HDL: Ternary Adder Tree

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This example describes a parameterized ternary adder tree in Verilog HDL. For devices which contain large lookup tables as combinational logic structures in logic element (LE) such as Stratix® II, structuring adder trees as ternary adder trees can give significant performance improvement.

Figure 1. Ternary adder tree top-level diagram.

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Table 1. Ternary Adder Tree Port Listing

Port Name Type Description
A, B, C, D, E Input Parameterized inputs to adder tree
CLK Input Clock
OUT Output Parameterized output of adder tree
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