Verilog HDL: Single-Port RAM

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This example describes a 64-bit x 8-bit single-port RAM design with common read and write addresses in Verilog HDL. Synthesis tools are able to detect single-port RAM designs in the HDL code and automatically infer either the altsyncram or the altdpram megafunctions, depending on the architecture of the target device.

Figure 1. Single-port RAM top-level diagram.

Download the files used in this example:

Port Name

Type

Description

data[7:0]

Input

8-bit data input

addr[5:0]

Input

6-bit address input

we

Input

Write enable input

clk

Input

Clock input

q[7:0]

Output

8-bit data output
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