This example describes a 64-bit x 8-bit single clock synchronous RAM design with different read and write addresses in Verilog HDL. Synthesis tools are able to detect single clock synchronous RAM designs in the HDL code and automatically infer either the altsyncram or altdpram megafunctions, depending on the architecture of the target device.
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Table 1. Single Clock Synchronous RAM Port Listing
| Port Name | Type | Description |
|---|---|---|
| data[7:0] | Input | 8-bit data input |
| read_addr[5:0] | Input | 6-bit read address input |
| write_addr[5:0] | Input | 6-bit write address input |
| we | Input | Write enable input |
| clk | Input | Clock input |
| q[7:0] | Output | 8-bit data output |