Verilog HDL: Signed Multiplier-Adder

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This example describes a 16-bit signed multiplier-adder design with pipeline registers in Verilog HDL. Synthesis tools are able to detect multiplier-adder designs in the HDL code and automatically infer the altmult_add megafunction to provide optimal results.

Figure 1. Signed multiply-adder top-level diagram.

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1. Signed Multiplier-Adder Port Listing

Port Name Type Description

dataa[15:0], datab[15:0],y

datac[15:0], datad[15:0]

 Input 16-bit data inputs
clock Input Clock input
aclr Input Asynchronous clear input
result[32:0] Output 33-bit data output
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