The Quartus® II software high-speed differential I/O design example consists of three megafunctions:
- LVDS receiver (altlvds_rx)
- Multiplier (lpm_mult)
- LVDS transmitter (altlvds_tx).
The LVDS receiver, multiplier, and LVDS transmitter modules are created using the Quartus® II software MegaWizard® Plug-In. They are connected as shown in Figure 1, which illustrates the performance of:
- Converting 840 megabits per second (Mbps) serial data into 8-bit parallel data using altlvds_rx
- Multiplication of the two 8-bit parallel data using lpm_mult
- Converting the parallel data coming out of the multiplier into serial data using altlvds_tx
The multiplier will be implemented in a dedicated digital signal processing (DSP) block within the Intel® Stratix® device. The motive behind this example is to show the data conversion. A testbench is created in Verilog and simulated using the ModelSim*-Intel® FPGA tool.
Download the files used in this example:
The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.
Table 1. Files Included in diff_io_top.zip
| Directory | File | Description |
|---|---|---|
| src | diff_io_top.v lvds_rx.v mult.v lvds_tx.v |
Top-level design file that instantiates the receiver, multiplier, and transmitter LVDS receiver generated by the MegaWizard Plug-In 8-bit multiplier generated by the MegaWizard Plug-In LVDS transmitter generated by the MegaWizard Plug-In |
| sim | testbench.y diff_io_top.vo diff_io_top.sdo comp_altera_lib.do comp_gate.do gate_sim.do Stratix library |
Instantiates the top-level module and consists of the test vectors Quartus II software-generated Verilog netlist to be used with the ModelSim tool Quartus II software-generated SDF timing file Script to compile the Stratix library Script to compile the testbench and the gate-level netlist Script to run the design in the ModelSim tool ModelSim compiled models |
Table 2. High-Speed Differential I/O Design Example Port Listing
| Port Name | Type | Description |
|---|---|---|
| rx_in[0] | Input | 1-bit unsigned serial input binary data |
| rx_in[1] | Input | 1-bit unsigned serial input binary data |
| rx_inclock | Input | Input clock with frequency of 105 MHz |
| tx_out[0] | Output | 1-bit unsigned serial output binary data |
| tx_out[1] | Output | 1-bit unsigned serial output binary data |
| tx_outclock | Output | Output clock from phase-locked loop (PLL) with frequency of 105 MHz |
Simulating the Design
- Invoke the ModelSim* 5.6c tool.
- Change directory to the location where the simulation files are located.
- Source the script gate_sim.do by using the command: VSIM > do gate_sim.do
Result of multiplication appears after 180 ns.
Related Links
For more information on using this example in your project, go to:
- The Mentor Graphics ModelSim* and QuestaSim Support chapter of volume 3 of the Quartus® II handbook