Verilog HDL: Binary Adder Tree

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This example describes a 16-bit binary adder tree in Verilog HDL. For devices with 4-input lookup tables in logic elements (LEs), using a binary adder tree structure can significantly improve performance.

Figure 1. Binary adder tree top-level diagram.

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The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1 lists the ports in the binary adder tree design.

Table 1. Binary Adder Tree Port Listing

Port Name Type Description
A[15:0], B[15:0], C[15:0], D[15:0], E[15:0] Input 16-bit data inputs
clk Input Clock input
out[15:0] Output 16-bit data output
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