Verilog HDL: 1x64 Shift Register

author-image

By

This example describes a single-bit wide, 64-bit long shift register in Verilog HDL. Synthesis tools detect groups of shift registers and infer altshift_taps megafunction depending on the target device architecture.

Figure 1. 1 x 64 shift register top-level diagram.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1 lists the ports and gives a description for each.

Table 1. 1x64 Shift Register Port Listing

Port Name Type Description
clk Input Clock
shift Input Shift enable input
sr_in Input Shift register input
sr_out Output Shift register input
View all Show less