Verification
Intel provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon® Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon® Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.
Designs targeted for the Intel® MAX® 10 device family and its development kits are available in the Design Store.
| Design Examples | Device Targeted | Development Kits Supported | Qsys Compliant | Quartus II Version |
|---|---|---|---|---|
| Nios® II: Avalon Verification IP Suite Design Example | - | - | X | 11.0 |
| Nios II: Debugging with System Console over TCP/IP | Cyclone® III | Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition | - | 12.0 |
| Nios II: Simulating Nios II Embedded Processor Designs | Stratix® II | Nios II Development Kit, Stratix II | X | 11.0 |
Simulation
Intel provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.
| Design Examples | Device Targeted | Development Kits Supported | Qsys Compliant | Quartus II Version |
|---|---|---|---|---|
| Nios II: Avalon Verification IP Suite Design Example | - | - | X | 11.0 |
| Nios II: Debugging with System Console over TCP/IP | Cyclone III | Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition | - | 12.0 |
| Nios II: Simulating Nios II Embedded Processor Designs | Stratix II | Nios II Development Kit, Stratix II | X | 11.0 |