This design example is a cost-effective, high-precision analog-to-digital converter (ADC) commonly used in wireless and audio applications, consisting of two major blocks: analog modulator and digital filter. The analog modulator over-samples and converts the analog signal into a stream of bits. The digital filter then converts the serial stream into digital number by decimation operation.
This design example shows an efficient and cost-effective way to implement the digital decimation filter with multi-stage partition method and use the time-division multiplexed (TDM) feature in DSP Builder Advanced Blockset to achieve both high-speed performance and low-resource usage.
Figure 1 shows the block diagram of a Sigma-Delta ADC with analog modulator that is modeled with a Simulink block and a digital decimation filter (implemented with a DSP Builder block).
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Specifications
Table 1 lists the specifications used to design the digital decimation filter.
Table 1. Specifications for the Digital Decimation Filter
Digital Decimation Filter Parameters |
Values |
|---|---|
Number of Channels |
8 |
Decimation Rate Change Factor |
64 |
Input Sample Rate |
3.072 Mbps |
Output Sample Rate (fs) |
48 KHz |
Output Data Width |
16 |
Passband Frequency |
0.423 fs |
Stopband Frequency |
0.5 fs |
Passband Ripple |
0.04 dB |
Clock Rate |
24.576 MHz |
Device Family |
Cyclone® III |
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