Configuration via Protocol
Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express (PCIe*) interface for various devices.
Configuration via Protocol Support provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, Cyclone® 10, Stratix® V and Arria® V devices.
Get additional support for Agilex™ 7 System Architecture, Agilex™ 5 System Architecture, and the Agilex™ 3 System Architecture, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGAs to easily meet the PCIe wake-up time requirement.
Table 1. CvP Documentation and Resources
Documentation |
Description |
|---|---|
| Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide | This document describes the CvP configuration scheme for Agilex™ 7 device family. |
| Agilex™ 5 Configuration via Protocol (CvP) Implementation User Guide | This document describes the CvP configuration scheme for Agilex™ 5 FPGAs. |
| Agilex™ 3 Configuration via Protocol (CvP) Implementation User Guide | This document describes the CvP configuration scheme for Agilex™ 3 FPGAs. |
| Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide | This document describes the CvP configuration scheme for Stratix® 10 device family. |
| Arria® 10 CvP Initialization and Partial Reconfiguration Over PCI Express User Guide | This user guide discusses the modes, topologies, features, design considerations, and software for CvP in 20 nm FPGAs. |
| Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide | This user guide discusses the modes, topologies, features, design considerations, and software for CvP. |
| FPGA Configuration via Protocol White Paper | This white paper describes how CvP helps your system meet the PCIe wake-up time requirement in 28 nm FPGAs. |
Table 2. CvP Drivers and Tools
| Driver and Tools | Description |
|---|---|
Configuration via Protocol (CvP) - Upstream Open Source CvP Driver in Linux Systems (14 nm and 10 nm devices)
|
This is the code for an open-source Linux* driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system. |
Configuration via Protocol (CvP) - Software driver code (28 nm and 20 nm devices)
|
This is the code for an open-source Linux driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system. |