Configuration via Protocol

Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express (PCIe*) interface for various devices.

The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGAs to easily meet the PCIe wake-up time requirement.

Table 1. CvP Documentation and Resources

Resources Documentation

Description
Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs This document describes the CvP configuration scheme for Agilex™ 5 FPGAs.
Agilex™ 7 device configuration via protocol (CvP) implementation user guide This document describes the CvP configuration scheme for Agilex™ 7 device family.
Stratix® 10 configuration via protocol (CvP) implementation user guide This document describes the CvP configuration scheme for Stratix® 10 device family.
Arria® 10 CvP initialization and partial reconfiguration over PCI Express user guide This user guide discusses the modes, topologies, features, design considerations, and software for CvP in 20 nm FPGAs.
Configuration via protocol (CvP) implementation in V-series FPGA devices user guide This user guide discusses the modes, topologies, features, design considerations, and software for CvP.
FPGA configuration via protocol white paper This white paper describes how CvP helps your system meet the PCIe wake-up time requirement in 28 nm FPGAs.
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Table 2. CvP Drivers and Tools

Driver and Tools Description
Configuration via Protocol (CvP) - Upstream Open Source CvP Driver in Linux Systems (14 nm and 10 nm devices) This is the code for an open-source Linux* driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system.

Configuration via Protocol (CvP) - Software driver code (28 nm and 20 nm devices)

  • Supported devices:
    • Arria® 10 FPGAs and SoC FPGAs
    • Cyclone® 10 GX FPGAs
    • Stratix® V FPGAs
    • Arria® V FPGAs and SoC FPGAs

This is the code for an open-source Linux driver to configure the core of an FPGA via CvP. You can use this open-source code as a reference when writing your own driver, or customize this driver to perform CvP operations on your system.
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