Passive Serial Configuration

Passive serial (PS) configuration can be performed using an Intel® FPGA download cable, an Intel FPGA configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Intel FPGA device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.

For more information, please refer to the configuration chapter of the relevant Intel FPGA device in the Configuration Handbook.

Configuration Methods

• Use a processor as an external host
• Use a MAX® series CPLD as an external host

Embedded Solutions

• MicroBlaster™ Software Driver
  
• Portable software driver used to configure an FPGA via a PS interface
• Works on a PC using a ByteBlaster™ II or ByteBlasterMV™ download cable
• Source code available for porting to an embedded system or other platform
• MicroBlaster Embedded Version
• Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board white paper
• Source code available for porting to an embedded or other platform

User Guide

• Parallel Flash Loader Intel® FPGA IP User Guide
• Method to program CFI flash memory devices through the JTAG interface and the logic to control configuration from the flash memory device to the FPGA

Reference Design

• MAX Series Configuration Controller Using Flash Memory white paper
  
• Using a MAX or MAX® II device as a configuration controller to configure Intel FPGAs from flash memory
• Source code in Verilog and VHDL