Description
In the Agilex™ 7 FPGA F and I series devices, only CLK_[T,B]_*_0 pins can directly drive Fabric-Feeding IOPLLs in the respective IO banks.
CLK_[T,B]_*_1 pins can drive Fabric_feeding IOPLLs in the same bank only if you select "Refclk source is the global clock" in the IOPLL IP.
Resolution
This information will be included in a future release of the Agilex™ 7 FPGA Clocking and PLL User Guide.