Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, when the number of lanes per converter device L parameter in the GTS JESD204B IP Parameter Editor is set to L = 6 or L = 8, the pma_cu_clk port has a width of 1 bit in the generated HDL code. However, for L = 6 or L = 8, the GTS Reset Sequencer IP necessitates a pma_cu_clk port width of 2 bits, which will cause a port width mismatch between the two ports.
When using Platform Designer to connect the pma_cu_clk ports from the GTS Reset Sequencer IP to the GTS JESD204B IP, an error will be shown in the System Messages console:
Error: jesd_gts_ss.jesd_gts_jesd204b.pma_cu_clk/jesd_gts_ss_intel_srcss_gts.o_pma_cu_clk: Signal clk has width 1 on jesd_gts_jesd204b.pma_cu_clk, but has width 2 on jesd_gts_ss_intel_srcss_gts.o_pma_cu_clk
This workaround is only applicable during IP generation.
1. In the IP Files, open the <IP name>.v file at the Project Navigator: Eg: <IP name>/synth/<IP name>.v
2. Edit the pma_cu_clk width manually by adding one bit as shown below:
3. Save and close <IP name>.v file
Altera® recommends installing the following patch in the Altera® Quartus® Prime Pro Edition Software version 24.3:
Download patch 0.02 for Windows (quartus-24.3-0.02-windows.exe)
Download patch 0.02 for Linux (quartus-24.3-0.02-linux.run)
Download the Readme for patch 0.02 (quartus-24.3-0.02-readme.txt)
After installing the patch, regenerate the GTS JESD204B IP via Platform Designer.
This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3.1.