Why do PCI Express links in the Agilex™ 5 E-Series devices fail link training after cold reset or fail to retrain after the reference clock to the transceiver TX PLL and CDR are resumed after a disruption?

To protect a transceiver reference clock buffer from aging and damage, it is turned off when there is no valid clock activity on the buffer. After the reference clock is brought up and stable at the buffer, users need to turn on the buffer by either reconfiguring the device or performing read and write operations to the reference clock buffer registers via the Avalon® Memory-Mapped interface.

For PCIe links in Agilex™ 5 devices, the reference clock buffers are turned off if the reference clocks driving transceiver TX PLL and CDR are unavailable before device configuration starts or are disrupted during PCIe link operation. When the reference clock becomes available, the buffers remain turned off without users manually turning them on. Hence, the PCIe links fail to come up.

A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.3.1. Download and install Patch 1.02fw from the appropriate link below.

• Download patch 1.02fw for Windows
• Download patch 1.02fw for Linux
• Download the Readme for patch 1.02fw

This problem will be fixed in a future release of the Quartus® Prime Pro Edition software. With this fix, reference clock buffers that are already off and turned on automatically when the reference clock is available.