Article ID: 000099314 Content Type: Product Information & Documentation Last Reviewed: 07/16/2024

​​​​​​​Which Agilex™ 5 IP features have limited hardware validation in the Quartus® Prime Pro Edition Software v24.2?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Quartus® Prime Pro Edition Software version 24.2 provides limited hardware support for Agilex™ 5 IPs or features as per the table below. Additionally the device models, bitstreams, and firmware for the devices are not finalized. 

     

    Known issues impacting specific functionality of Agilex™ 5 can be referred to Agilex 5 Knowledge base Article Search.

     

     

    Resolution

    Device Features/IP

    IP/Functions Not Validated in Hardware for 24.2

    Transceiver

    GTS PMA/FEC Direct PHY FPGA IP

    PCS Direct Mode
    Tx/Rx Simplex
    "Analog Parameter" options (except default values)

    GTS Reset Sequencer FPGA IP

    GTS System PLL Clocks FPGA IP

    GTS Transceiver Toolkit

    FEC options

    Ethernet

    GTS Ethernet FPGA Hard IP

    SyncE, MAC Features (SFC, PFC, CRC), Manual Adaptation

    Client Loopback in ED

    Low Latency 40G Ethernet FPGA IP

    SyncE, MAC Features (SFC, PFC, CRC).

    Triple-Speed Ethernet FPGA IP

    Loopback on MII/GMII, RGMII Interface, Flow Control, Align-Packet Header with 32-bit

    Ethernet Toolkit

    Multi instances without PTP

    External loopback with PTP

    PCIe

    GTS AXI Streaming FPGA IP for PCI Express

    Example design,PTM

    Interlaken

    GTS Interlaken FPGA IP

    IP not validated in hardware

    JESD204

    JESD204C GTS FPGA IP

    IP not validated in hardware

    PHYLITE

    PHY Lite for parallel interfaces FPGA IP

    IP not validated in hardware

    HPS 

    Processors and Peripherals

    Embedded software readiness

    Video

    DisplayPort FPGA IO

    IP not validated in hardware

    GTS DisplayPort Phy Altera FPGA IP

    IP not validated in hardware

    GTS HDMI FPGA IP 

    IP not validated in hardware

    Processors and Peripherals GTS SDI II FPGA IP

    IP not validated in hardware