Why are my output pins not recognized in Quartus® Pin Planner after Analysis & Synthesis?

Due to a problem in Quartus® Prime Pro Edition Software version 23.3 and later, output signals without wire assignments in Verilog HDL are not recognized by Pin Planner after Analysis & Synthesis. In earlier versions of Quartus® Prime Pro Edition Software, wire assignments were not required.

To work around this problem, download and install the patch for the Quartus® Prime Pro Edition Software version 23.3.

Download and install Patch 0.45 for 23.3 from the appropriate link below.

• Download the version 23.3 patch 0.45 for Windows (.exe)
• Download the version 23.3 patch 0.45 for Linux (.run)
• Download the Readme for Quartus® Prime Pro Edition Software version 23.3 (.txt)

This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.