Article ID: 000097794 Content Type: Troubleshooting Last Reviewed: 04/09/2024

Why do writes to an M20K fail after a Partial Reconfiguration?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and later, you might see a functional failure when writing to an M20K RAM after Partial Reconfiguration. This problem only occurs in design targets an Agilex™ 7 F/I-Series devices and either of these conditions

    • The Compiler Optimization Mode is not set to Performance
    • The design has 2 or more abutting PR partitions that share the same clock.

     

    Resolution

    To workaround this problem, perform these options

    • Recompile the design with Compiler Optimization Mode set to one of the Performance options.

     

     

    • Ensure there is a separation (at least one row/column space) between abutting PR partition routing regions for the designs with more than one PR region.

     

    Note: This restriction does not apply to Agilex™ 7 M-series production devices.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series