Why do I see bit errors on the TX side of my F-Tile PMA/FEC Direct PHY Intel® FPGA IP variant when it is configured for 100G-4 PMA Direct mode on FGT transceivers?

Due to a problem in Intel® Quartus® Prime Pro Edition Software versions 23.1 to 23.3, you might encounter bit errors on the TX side of your F-Tile PMA/FEC Direct PHY Intel® FPGA IP variant when configured for 100G-4 PMA Direct mode on FGT transceivers if the variant is physically placed on the F-tile so that it is using the 200G Hard IP of the F-tile.

This problem does not happen on the 100G-4 FEC direct variant or any other variants, regardless of rate or mode.
In order to determine if your 100G-4 PMA direct variant is using the 200G Hard IP of the F-tile, perform the following steps:

1. )    Open the <project_name>.tlg.rpt
2. )    Locate your transmit channel and determine if it has been placed in the 200G Hard IP of the tile

For example:
-- BB_F_EHIP_TX                           
u0|example|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx

-- location                                 ; z1577b_x393_y0_n0.ehip200g_st_x2_0_tx

To work around  this problem, perform the following reads and writes on the “reconfig_pdp” bus of the IP:

1. )    Read register 0x6000 for all (4) channels of the 100G variant
2. )    Write bits [6:3] of the register to 4’b0010. Leave the remaining bits of the register unchanged

For example, if register 0x6000 reads back 0x00380080, then write this register with 0x00380090 value as shown below

% reg_write 0x06000 0x00380090 
% reg_write 0x16000 0x00380090 
% reg_write 0x26000 0x00380090 
% reg_write 0x36000 0x00380090 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.