Article ID: 000096286 Content Type: Troubleshooting Last Reviewed: 04/17/2024

Why does the F-Tile FHT transceiver design fail in the “Support Logic Generation” phase when the “Select FHT Lane PLL refclk source” parameter is set to "REF_TO_GND" as default?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, you might see failure in the “Support Logic Generation” phase when the Select FHT Lane PLL refclk source parameter is set to REF_TO_GND as default.

     

    Resolution

    To work around this problem in the Quartus® Prime Pro Edition Software version 23.2, select FHT Lane PLL refclk source to either PLL_100_MHZ or PLL_156_MHZ.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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