Article ID: 000096078 Content Type: Error Messages Last Reviewed: 04/23/2024

Why does the Memory Subsystem FPGA IP fail while generating the example design?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software, you might see the following error when generating an example design for the Memory Subsystem FPGA IP v1.0.0

    "mem_ss_0: An error has occurred when generating the sim example design fileset. See sim/make_sim_design.log for details"

    This IP is still under development and is not recommended for design or simulation.

     

     

    Resolution

    This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.3.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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