Internal Error: Sub-system: EPEO, File: /quartus/power/epeo/epeo_writer2.cpp, Line: <number>

Due to a problem in Quartus® Prime Pro Edition Software version 23.2 and earlier, you may see this internal error when Power Analyzer is executed in Agilex™ 7 device.  The error is caused by inappropriate Synopsis Design Constraints (SDC) descriptions for the Reset Release FPGA IP.

Line: <number> in the error message depends on the version of Quartus® Prime Pro Edition Software. 

When using version 22.4 and earlier, it is Line: 201. 

When using version 23.1 and later, it is Line: 183.

To work around the error, remove the following SDC file from the file list of SDC files for Timing Analyzer before executing Power Analyzer.

• reset_release/altera_s10_user_rst_clkgate_<number>/synth/altera_s10_user_rst_clkgate_fm.sdc

Please note that <number> in the file path depends on the Quartus® Prime Pro Edition Software version.

To exclude the above SDC file from Timing Analyzer, use the following steps

1. Open Settings window
2. Select Timing Analyzer in the Category panel of the Settings window
3. Remove <relative path from project directory>/reset_release.ip from the file list of SDC files to include in the project 

This problem will be fixed in a future version of Quartus® Prime Pro Edition Software.