Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.2, you might see this internal error when using a locally routed clock for an M20K in a partial reconfiguration (PR) region during a PR - persona implementation revision compile targetting an Intel Agilex® 7 F/I-series FPGA device.
Resolution
To workaround this problem, ensure that the clock is promoted to a global signal before entering the PR partition. Locally routed clocks are not permitted with M20Ks in PR partitions.
This problem will be fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.3 by replacing the internal error with an error message.
Note: This restriction does not apply to Intel Agilex® 7 M-series production devices.