In the Quartus® Prime Pro Edition Software version 23.2 and later, you might see this error when a signal routed using global signal resources is used as an input to a soft logic that requires transferring to local routing (e.g., a clock multiplexer implemented in a LUT). This error only occurs in Agilex™ 7 F/I-series FPGA devices.
Driving such a soft logic with a globally routed signal is not permitted in a partial reconfiguration (PR) partition.
To avoid this error, separate the entry port of the signal at the PR partition into two entry ports: one port that can remain locally routed and the other port that can be globally routed.
Note that the clocks used to drive M20K RAMs in the PR region must be globally routed in Agilex™ 7 F/I-series FPGA devices, so they must remain on the globally routed resources.
This scenario is not permitted in the PR partition and results in a Local / Global fanout Error.
The problem should be fixed as illustrated in the below diagram.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.