Article ID: 000095626 Content Type: Troubleshooting Last Reviewed: 06/13/2024

Why does the Serial Lite III Streaming FPGA IP design simulation fail using Questa*- FPGA Edition Software version 2023.1?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Questa*-Intel® FPGA Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, you might observe Verilog and VHDL simulation failures for the Serial Lite III Streaming FPGA IP design with Standard Clocking Mode for the Arria® 10 and Cyclone® 10 devices when using the latest version 2023.1 of Questa*- FPGA Edition Software.

    Resolution

    To avoid this simulation failure, you can use the previous Questa*- FPGA Edition Software version 2022.4.

     

    Related Products

    This article applies to 2 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 GX FPGA