Article ID: 000095589 Content Type: Errata Last Reviewed: 11/12/2024

Why does the F-Tile variant with a combination of PTP and non-PTP enabled ports within the Ethernet Subsystem FPGA IP fail to simulate correctly?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.2,  the F-Tile variants with a combination of PTP and non-PTP enabled ports within the Ethernet Subsystem FPGA IP will fail to simulate properly.

     

     

    Resolution

    There is no workaround for this problem. 

    This problem had been fixed in version 24.2 of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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