Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4, this error will be seen when using Questa*-Intel® FPGA Edition to simulate a design example that instantiates the PHY Lite for Parallel Interfaces Intel Agilex® FPGA IP.
To work around this problem, perform the following steps:
- Open msim_setup.tcl file under .../sim/ed_sim/mentor folder.
- Modify the following command:
eval vsim -voptargs=+acc $elabcommand
to
eval vsim -suppress 2732 -voptargs=+acc $elabcommand
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.