Why do I get an error when compiling the H-Tile Multichannel DMA Intel® FPGA IP for PCI Express* Design Example with 1 channel configuration ?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, an error will be observed when compiling the H-Tile Multichannel DMA Intel® FPGA IP for PCI Express* Design Example with 1 DMA Channel configuration.

Verilog HDL error at intel_pcie_prefetch_desc_fifo.sv(0): part-select direction is opposite from prefix index direction

Verilog HDL or VHDL error at intel_pcie_prefetch_desc_fifo.sv(0): index ** is out of range (**:**) for ‘**’

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.