You might see Intel® Quartus® Tile Logic Generation Critical Warning messages like the following in your Intel Agilex® 7 device with F-Tile transceivers when using the Intel® Quartus® Prime Pro Edition Software version 23.1.
Critical Warning(23469): The block <path>|x_bb_f_ux_tx did not set the following parameters
Info(23470): Parameter txeq_main_tap
Info(23470): Parameter txeq_post_tap_1
Info(23470): Parameter txeq_pre_tap_1
Info(23470): Parameter txeq_pre_tap_2
Critical Warning(23469): The block <path>|x_bb_f_ux_rx did not set the following parameters
Info(23470): Parameter rxeq_dfe_data_tap_1
Info(23470): Parameter rxeq_hf_boost
Info(23470): Parameter rxeq_vga_gain
To remove the transmitter warnings, you should add Quartus Settings File (QSF) constraints according to your channel loss requirements. For example you could enter:
set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=35" -to <pin_name>
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=5" -to <pin_name>
set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to <pin_name>
set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to <pin_name>
Most Intel F-Tile transceiver IP like those listed below use automatic RX adaptation. In this case you can safely ignore the rxeq_dfe_data_tap_1, rxeq_hf_boost, and rxeq_vga_gain critical warnings which are used for manual RX equalization. If you want to remove these critical warnings, you can add QSF assignments according to the table below which were determined from the Intel IP design examples in Intel® Quartus® Prime Pro Edition Software version 23.1.
| rxeq_dfe_data_tap_1 | rxeq_hf_boost | rxeq_vga_gain | |
| F-Tile Ethernet IntelFPGA Hard IP | 0 | 0 | 60 |
| F-Tile JESD204C Intel FPGA IP | 0 | 0 | 60 |
| F-Tile Serial Lite IV Intel FPGA IP | 0 | 0 | 60 |
| F-Tile Interlaken Intel FPGA IP | 0 | 0 | 60 |
| F-Tile CPRI PHY Intel FPGA IP | 0 | 0 | 60 |
| F-Tile PMA/FEC DirectPHY Multirate Design Example | 0 | 0 | 60 |
| F-Tile Ethernet Multirate Design Example | 0 | 0 | 60 |
| F-Tile CPRI Multirate Design Example | 0 | 0 | 60 |
| F-Tile HDMI Intel FPGA IP | 0 | 0 | 60 |
| F-Tile SDI II Intel FPGA IP | 0 | 0 | 60 |
| F-Tile DisplayPort Intel FPGA IP | 0 | 0 | 37 |
For example, the following would be used for the F-Tile Ethernet Intel FPGA Hard IP.
set_instance_assignment -name HSSI_PARAMETER "rxeq_dfe_data_tap_1=0" -to <pin_name>
set_instance_assignment -name HSSI_PARAMETER "rxeq_hf_boost=0" -to <pin_name>
set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=60" -to <pin_name>
You may see an Intel® Quartus® Tile Logic Generation (QTLG) error if you use different values from the table.
This problem will be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.