Why does the Intel Agilex® 7 FPGA DDR4 IP EMIF Traffic Generator 2.0 incorrectly assert the fail signal?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.4, when the user has configured TG2 to enable WORM mode, return to start address, and the number of loops is greater than 1, if a failure is observed by TG2, it will not assert a failure signal and timeout will occur. This occurs when TG2 enters the targeted reads stage to perform another read to the failing address, and does not leave the stage.

This problem is fixed starting in the Intel® Quartus® Prime Pro Edition Software version 21.1.