The reason for low write performance on the write response path in AXI backpressure mode is that when the AXI backpressure is enabled, the desirable write throughput numbers cannot be achieved.
In this mode, a soft-logic read response FIFO is instantiated, but it is currently too shallow to absorb bursts of write responses, resulting in the Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP being back pressured. Internal to the HBMC, this backpressure results in backpressure on the write command channels, limiting overall system throughput.
To work around this issue, increase the depth of the write response FIFO from 16 to 32. This increases the FIFO counter width by 1 bit. However, there is no impact on the area.
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2 onwards.