Article ID: 000094959 Content Type: Error Messages Last Reviewed: 05/18/2023

Why there is an error in Intel® Quartus® Prime Pro Edition Software version 21.1 for Intel Agilex® 7 DDR4 IP EMIF Traffic Generator 2 when configured to have 1 read cycle and 1 write cycle within a loop?

Environment

  • Intel® Quartus® Prime Design Software
  • Intel® FPGA Programming Software
  • External Memory Interfaces Debug Component Intel® FPGA IP
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    Description

    You may encounter an error in Intel Agilex® 7 DDR4 IP EMIF Traffic Generator 2 when configured to have 1 read cycle and 1 write cycle within a Loop with initializing the read-write/loop idle counters. Due to incorrect idle periods from the write cycle to the read cycle and vice versa. 

     

    To work around this issue, change how the counters are initialized after a new loop.

     

     

    Resolution

    This problem is planned to be fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4 onwards.

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