Article ID: 000094923 Content Type: Error Messages Last Reviewed: 05/19/2023

Why does the Intel® Stratix®10 Low Latency Ethernet 10G MAC Intel® FPGA IP Example Design simulation fail?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 or earlier, the following error will appear in the simulation when using the design example generated by the 10M/100M/1G/2.5G/5G/10G(USXGMII) preset.


    # ** Error: ../models/altera_eth_top.sv(128): Module 'altera_eth_top_auto_tiles' is not defined.

    Resolution

    There is no workaround for this problem.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.
     

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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