Why do I see FCS or CRC errors on a link partner or Ethernet tester when the “Packet Client Loopback” is enabled on my F-tile Ethernet Intel® FPGA Hard IP design example?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, you might see FCS or CRC errors on a link partner or Ethernet tester when the “Packet Client Loopback” is enabled on the design example of the F-tile Ethernet Intel® FPGA Hard IP. 

To work around this problem,  write 32’h0000_0000 to the cfg_rom_pkt_gap_addr (offset 0x1C) register. For the single IP instance design example, this register can be found at absolute offset 0x0010_001C. 
This problem has been fixed starting from version 23.2 of the Intel® Quartus® Prime Pro Edition Software.