Article ID: 000094703 Content Type: Troubleshooting Last Reviewed: 05/02/2023

Why does Intel Agilex® 7 SoC FPGA fail to access the whole HPS EMIF memory space?

Environment

  • Intel® Quartus® Prime Pro Edition
  • u-boot-socfpga

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    Description

    Due to a problem with u-boot-spl(u-boot-socfpga-v2022.07 and previous version) for Intel Agilex® 7 SoC FPGA, when HPS EMIF is set to Quarter Rate in HPS EMIF IP GUI and Half Rate Converter (HRC) is enabled automatically by HPS EMIF, you may see that the higher half memory space is overlapped with the lower half memory space.

    The problem would result in the memory read and write failure in U-Boot, Linux, or system boot failure.

    For example, if the HPS EMIF is set to be 2GB, you will always get the same data from the address X in lower 1GB and the address X+0x4000_0000 in higher 1GB, such as 0x1000_0000 and 0x5000_0000. Both HPS and the F2H interface master will see the same symptom.

    Resolution

    The problem has been fixed in u-boot-socfpga-v2022.10. You can update U-Boot to this version or the latest version.

    For u-boot-socfpga-v2022.07 and the previous version, you can apply the following change to fix it:

    https://github.com/altera-opensource/u-boot-socfpga/commit/9357894a21f4125f14db4e28910b371a4031a818

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