Article ID: 000094608 Content Type: Troubleshooting Last Reviewed: 10/31/2023

Why do I see Critical Warning(23469) messages for my Intel Agilex® 7 device with F-Tile Avalon Streaming Intel® FPGA IP for PCI Express* design when using the Intel® Quartus® Prime Pro Edition Software version 23.1?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You might see Quartus® Tile Logic Generation Critical Warning messages like the following in your Intel Agilex® 7 device with F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* design when using the Intel® Quartus® Prime Pro Edition Software version 23.1.

     

    Critical Warning(23469): The block dut|dut|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_ux_inst0|x_bb_f_ux_tx did not set the following parameters

                    Info(23470): Parameter txeq_main_tap

                    Info(23470): Parameter txeq_post_tap_1

                    Info(23470): Parameter txeq_pre_tap_1

                    Info(23470): Parameter txeq_pre_tap_2

    Critical Warning(23469): The block dut|dut|pcie_hip_top_f_inst|pcie_hip_bb_f_inst|f_ux_inst0|x_bb_f_ux_rx did not set the following parameters

                    Info(23470): Parameter rx_ac_couple_enable

                    Info(23470): Parameter rx_onchip_termination

                    Info(23470): Parameter rxeq_dfe_data_tap_1

                    Info(23470): Parameter rxeq_hf_boost

                    Info(23470): Parameter rxeq_vga_gain

    Resolution

    To remove the transmitter warnings, you should add constraints similar to the following. Note that the Avalon® Streaming Intel® FPGA IP for PCI Express* will overwrite these values during the link training process.

     

    set_instance_assignment -name HSSI_PARAMETER "txeq_main_tap=0" -to hip_serial_tx_p_out0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_1=0" -to hip_serial_tx_p_out0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "txeq_pre_tap_2=0" -to hip_serial_tx_p_out0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "txeq_post_tap_1=0" -to hip_serial_tx_p_out0 -entity pcie_ed

     

    To remove the receiver warnings, you should add constraints similar to the following.

     

    set_instance_assignment -name HSSI_PARAMETER "rxeq_dfe_data_tap_1=0" -to hip_serial_rx_p_in0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "rxeq_hf_boost=32" -to hip_serial_rx_p_in0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "rxeq_vga_gain=32" -to hip_serial_rx_p_in0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "rx_ac_couple_enable=ENABLE" -to hip_serial_rx_p_in0 -entity pcie_ed

    set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination=RX_ONCHIP_TERMINATION_R_2" -to hip_serial_rx_p_in0 -entity pcie_ed

     

    This problem will be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs