Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1, AXI-lite register accesses to the PTP packet parser of the Ethernet Subsystem Intel® FPGA IP will fail in 10G Asynchronous Clocking Mode if the AXI-ST data path clock is slower than the AXI-Lite clock.
Resolution
To work around this problem, ensure that the AXI-Lite clock is slower than the AXI-ST data path clock.
This problem will be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.