Article ID: 000094408 Content Type: Troubleshooting Last Reviewed: 12/02/2024

Why does the Serial Lite III Streaming FPGA IP design VHDL simulation fail using QuestaSim and Questa*- FPGA Edition Software?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.1, you might observe VHDL simulation failures for the Serial Lite III Streaming IP design with Standard Clocking Mode for the Stratix® 10 L/H-tile devices when using the latest version of QuestaSim and Questa*- FPGA Edition Software.

    Resolution

    To avoid this simulation failure, you can use the previous Questa Simulator version 2022.1.

    This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 AX SoC FPGA
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.