Article ID: 000094247 Content Type: Errata Last Reviewed: 11/28/2023

Why does the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fail to simulate when using the Cadence Xcelium* simulator?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® CPRI
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and earlier, you might see the CPRI Intel® FPGA IP Design Example for 24G variants with the Intel® Stratix® 10 L/H-Tile device fails to simulate when using the Cadence Xcelium* simulator.

    Resolution

    There is no workaround for this problem.
    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
     

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

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