Why are there functional failures when using some Intel Agilex® FPGAs F-Series -4F devices in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3 and earlier, you might see functional errors in Intel Agilex® FPGAs F-Series with a -4F speed grade. This problem occurs because of a discrepancy in the timing model for some of these devices at 0°C.

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4

If your project is still in the design phase and you are using the Intel® Quartus® Prime Pro Edition Software version 22.3 or earlier, or if you cannot export your design. Migrate your design to the Intel® Quartus® Prime Pro Edition Software version 22.4 or later following the next steps:

1. Open the original project in the Intel® Quartus® Prime Edition Software 22.4 or later. Click Yes if prompted to open a project created with a different software version.
2. Continue with the design process.

If you are targeting the Intel® Quartus® Prime Pro Edition Software version, 22.3 or earlier, and your project is finalized and in the production phase, follow steps (1) to (8):

1. Open the original project on the targeted Intel Quartus Prime Pro Edition Software version.
2. Export the final compilation results of your project by clicking Project > Export Design and selecting the final snapshot.
3. Close the design.
4. Open the original project in the Intel Quartus Prime Pro Edition Software version 22.4 or later, and click Yes if prompted to open a project created with a different software version.
5. Click on Project > Import Design and specify the final version of the database file. Turn on overwrite existing project's databases to remove previous results.
6. Run a signoff timing analysis by running Processing > Start > Start Timing Analysis (signoff)
   • If the design is affected, you will see new timing issues. Proceed to step (7).
   • If the design passes timing analysis, no further action is required.
7. Run a full compilation of your project by clicking Processing > Start Compilation.
   • If the timing issues have been solved, no further action is required, and you should use the new configuration file.
   • If you still see timing issues in the design, proceed to step 8.
8. Optimize your design for timing closure and recompile your design until the design has met timing requirements.
   • In some instances, compiling across multiple seeds might facilitate timing closure.