The L- and H-Tile Transceiver Native PHY Intel® Stratix® 10 IP rx_pma_clkslip and rx_bitslip functions can both be used for transceiver RX word alignment on the Intel® Stratix® 10 L-Tile and H-Tile devices.
The rx_pma_clkslip port acts on the physical medium attachment (PMA). When asserted it causes the deserializer to either skip one serial bit or pauses the serial clock for one cycle to achieve word alignment. The paused data feeds into the optional gearbox.
The rx_bitslip port acts on the physical coding sublayer (PCS). When asserted The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. The bit slipping is seen on the output of the gearbox.
When using the gearbox it may typically be used in 40:66 bit mode. If you use the rx_pma_clkslip port to pause data on the 40 bit domain, this may result in a lack of word alignment on the 66 bit domain.
Use the L- and H-Tile Transceiver Native PHY Intel® Stratix® 10 IP rx_bitslip port for transceiver configurations that use a gearbox.