Why does the 50G-1 variant of the F-Tile PMA/FEC Direct PHY Multirate Design Example encounter the assertion of verifier_error signal during the simulation run after completing the dynamic reconfiguration transition to PMA Direct 50G?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, users may encounter the assertion of verifier_error with the following message "data_error is detected at <simulation time>ns, PRBS Checker detected the error" during the simulation run after completing the dynamic reconfiguration transition to PMA Direct 50G. 

The workaround would require an update in the RTL of a design example component (testwrap_pma_direct.sv).

1. Open the file testwrap_pma_direct.sv located in the common folder.
2. Go to line #361.
3. Replace 

"enable_rx_verifier[i] = (enable_rx_verifier[i] == 1) ? 1 : rx_parallel_data[38+i*width_multiplier*80] & rx_parallel_data[118+i*width_multiplier*80] & rx_parallel_data[78+i*width_multiplier*80] & rx_parallel_data[79+i*width_multiplier*80] & rx_parallel_data[158+i*width_multiplier*80] & rx_parallel_data[159+i*width_multiplier*80];" 

With

"enable_rx_verifier[i] = rx_parallel_data[38+i*width_multiplier*80] & rx_parallel_data[118+i*width_multiplier*80] & rx_parallel_data[79+i*width_multiplier*80] make s& rx_parallel_data[159+i*width_multiplier*80];"

4. Save & close the file testwrap_pma_direct.sv

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 22.4.