Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.3, you might see an unconstrained clock derived from the Clock Divider in the Timing Analyzer, when using F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP if multiple F-Tiles are enabled and the Clock Source option in the GUI is configured as Clock Divider mode.
To work around this problem, modify the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express IP .sdc as follows:
Example:
create_generated_clock -name adapter_clk -source *|hdpldadapt_rx_chnl_5|pld_pcs_rx_clk_out1_dcm -master_clock [get_clocks ${ip_inst_name}*|rx_clkout|ch5] -multiply_by 1 -divide_by 2 [get_registers ${ip_inst_name}*|g_halfrate_inst.g_clkdiv_inst.pcie_clk_divider_inst~div_reg] -add
set_clock_groups -asynchronous -group [get_clocks ${ip_inst_name}*|rx_clkout|ch5] -group [get_clocks adapter_clk]
Change to:
create_generated_clock -source *|hdpldadapt_rx_chnl_5|pld_pcs_rx_clk_out1_dcm -master_clock [get_clocks ${ip_inst_name}*|rx_clkout|ch5] -multiply_by 1 -divide_by 2 [get_registers ${ip_inst_name}*|g_halfrate_inst.g_clkdiv_inst.pcie_clk_divider_inst~div_reg] -add
set_clock_groups -asynchronous -group [get_clocks ${ip_inst_name}*|rx_clkout|ch5] -group [get_clocks ${ip_inst_name}*|g_halfrate_inst.g_clkdiv_inst.pcie_clk_divider_inst~div_reg]
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.4.