Why does the design example for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP fail to function in hardware with internal serial loopback enabled?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the design example for the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP will fail to function correctly in hardware with internal serial loopback enabled.

This problem will affect all FGT variants of the design example, regardless of intellectual property (IP) type.

To work around this problem in hardware, first perform the following steps to confirm that the design example is running in internal serial loopback mode:

1.)    Navigate to <example design directory>/hardware_test_design/hwtest/src.

2.)    Open the parameter.tcl file and verify that the “loopback mode” parameter is set to 1 as shown below:

set loopback_mode 1

3.)    If the parameter is not set to 1, then the design example is running in external loopback mode and this solution does not apply. If the parameter is set to 1, then proceed as shown below:

4.)    Navigate to <example design directory>/hardware_test_design/hwtest/tests

5.)    For the Ethernet variants, open the ftile_eth_dr_test.tcl file.
         For the CPRI variants, open the ftile_cpri_dr_test.tcl file.
         For the Direct Phy variants, open the ftile_dphy_dr_test.tcl file.
         Regardless of variant, the workaround remains the same.

6.)    Locate and change the following lines:

From
    if {$loopback_mode == 1}  {
        set_ilb $NUM_CHANNELS 1
    } else {
        #set_ilb $NUM_CHANNELS 0
    }
    
To
    if {$loopback_mode == 1}  {
        set_ilb $NUM_CHANNELS 0
    }

7.)    Save the file.

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.4.