Article ID: 000092512 Content Type: Errata Last Reviewed: 09/04/2023

Why does my F-tile Ethernet Intel® FPGA Hard IP design example simulation fail using the Questa*-Intel® FPGA Edition simulator?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Questa*-Intel® FPGA Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, 22.3, and 22.4, you might see the F-tile Ethernet Intel® FPGA Hard IP design example simulation gets stuck at the reset sequence using the Questa*-Intel® FPGA Edition simulator.

    Resolution

    There is no workaround. You can use other simulators to run the simulation. For example, ModelSim* SE or QuestaSim*.

    This problem is fixed in version 23.1 of Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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