Why do I see an error while using the Xcelium* simulator when simulating non-AXI F-tile SDI II Intel® FPGA IP design example in VHDL file format?

When simulating non-AXI F-tile SDI II Intel® FPGA IP design example in VHDL file format using Xcelium simulator, you might see the following error messages as below:

• xmvhdl_p: *e,vlflnd (.sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_dqk73jq.vhd,751): verilog port (sdi_tr_du_sys_rx_phy_directphy_f_sr_wrapper_200_vt6seca.tx_coreclkin) of mode input requires association in implicit map aspect.
• xmvhdl_p: *e,vlflnd (.sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_dqk73jq.vhd,751): verilog port (sdi_tr_du_sys_rx_phy_directphy_f_sr_wrapper_200_vt6seca.tx_cadence_fast_clk) of mode input requires association in implicit map aspect.
• xmvhdl_p: *e,vlflnd (.sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_dqk73jq.vhd,751): verilog port (sdi_tr_du_sys_rx_phy_directphy_f_sr_wrapper_200_vt6seca.tx_cadence_slow_clk) of mode input requires association in implicit map aspect.
• xmvhdl_p: *e,vlflnd (.sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_dqk73jq.vhd,751): verilog port (sdi_tr_du_sys_rx_phy_directphy_f_sr_wrapper_200_vt6seca.tx_pll_refclk_link) of mode input requires association in implicit map aspect.
• xmvhdl_p: *e,vlflnd (.sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_wvmgbji.vhd,720): verilog port (sdi_tr_du_sys_rx_phy_directphy_f_sr_wrapper_200_sqqzlai.tx_pll_refclk_link) of mode input requires association in implicit map aspect.
• xmelab: *e,cuvmur (sdi_tr_du_sys_rx_phy_directphy_f_dr_200_fwyfaxa.sv,1335|84): instance 'tb_top.du_inst.sdi_tr_du_sys_inst:rx_phy:rx_phy.u_base_profile' of design unit 'sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_dqk73jq' is unresolved in 'directphy_f_dr_200.sdi_tr_du_sys_rx_phy_directphy_f_dr_200_fwyfaxa:module'.
• xmelab: *e,cuvmur (sdi_tr_du_sys_rx_phy_directphy_f_dr_200_fwyfaxa.sv,1367|90): instance 'tb_top.du_inst.sdi_tr_du_sys_inst:rx_phy:rx_phy.u_sec_profile1' of design unit 'sdi_tr_du_sys_rx_phy_directphy_f_dr_directphy_f_sr_wrapper_200_wvmgbji' is unresolved in 'directphy_f_dr_200.sdi_tr_du_sys_rx_phy_directphy_f_dr_200_fwyfaxa:module'.

This problem occurs because some ports are missing when the F-tile PMA/FEC Direct PHY Multirate Intel® FPGA IP is integrated into the F-tile SDI II Intel FPGA IP design example.

This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition Software version 22.4.