Description
Due to a problem in the Intel® Quartus® Prime Pro Edition software version 22.2, you may see this error during compilation with enabled Design Netlist Infrastructure (DNI) flow. This error may be seen on Intel Agilex® 7 FPGA devices using the HDMI Intel® FPGA IP.
Resolution
To work around this problem, follow these steps:
- Download the bitec-dd.zip file.
- Unzip the file to obtain the bitec_dd.v file and put it in the project directory.
- Add the following assignment to the end of the QSF:
set_global_assignment -name VERILOG_FILE bitec_dd.v -library altera_hdmi_1970
This problem is fixed beginning with version 22.3 of the Intel® Quartus® Prime Pro Edition Software.