Why isn't the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP compliant to the PCS transmit code group-state diagram written in the IEEE 802.3 Clause 36 when sending /I2/ Ordered Set?

Due to a problem in the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP, you might see the incorrect running disparity /I2/ Ordered Set in 1GbE mode.

According to the IEEE 802.3 Clause 36, /I2/ Ordered Set should be /K28.5-/D16.2+/ during IDLE duration.

However, the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP may generate an inverted running disparity of /I2/ Ordered Set which is /K28.5+/D16.2-/.

A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.2.

Download and install Patch 0.45 from the following links:

• Patch Intel® Quartus® Prime Pro Edition Software version 21.2 Patch 0.45 for Windows (.exe)
• Patch Intel® Quartus® Prime Pro Edition Software version 21.2 Patch 0.45 for Linux (.run)
• Readme for Intel® Quartus® Prime Pro Edition Software version 21.2 Patch 0.45 (.txt)

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3.