Why there is a Data loss on  Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP write response path in non-AXI backpressure mode?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 21.4 and 22.1, data loss on the write response path in non-AXI backpressure mode is expected due to the below reasons:

When AXI backpressure is not enabled in Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP, write responses may be lost. The reason is that the fabric can potentially receive two write responses in a single cycle.

In non-backpressure mode, there is only a cycle’s worth of read response buffering. Data loss occurs when there are two back-to-back cycles in which a pair of write responses are received. The issue is most prevalent when the fabric clock is relatively low. Even though that reduces the write command rate at the interface, if a refresh cycle causes a lot of write commands to be buffered by the Intel® Stratix® 10 MX/NX FPGA BMC devices, there will be a corresponding flood of responses once the refresh has completed.

It is recommended to instantiate the same FIFO on Intel® Stratix® 10 MX/NX FPGA High Bandwidth Memory (HBM2) IP as for AXI4 compliant backpressure handling. This does have an area penalty, but each pseudo channel's FIFO requires only one MLAB (+ some ALMs for counters).
 
This problem is currently scheduled to be resolved in a future release of the Intel® Quartus® Prime Pro Edition Software.